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DRF1200
(R) 15V, 13A, 30MHz
MOSFET Driver Hybrid
The DRF1200 MOSFET driver hybrid. This hybrid includes a high power gate driver and the power MOSFET. It was designed to provide the system designer increased flexibility and lowered cost over a non-integrated solution.
DRIVER FEATURES
* Switching Frequency: DC TO 30MHz * Low Pulse Width Distortion * Single Power Supply * 3V CMOS Schmitt Trigger Input 1V Hysteresis * Drivers > 3nF
MOSFET FEATURES
* Switching Frequency: DC TO 30MHz * Switching Speed 3-4ns * BVds = 1kV * Ids = 13A avg. * Rds(on) 1 Ohm * PD = 350W
TYPICAL APPLICATIONS
* Class C, D and E RF Generators * Switch Mode Power Amplifiers * Pulse Generators * Ultrasound Transducer Drivers * Acoustic Optical Modulators
Driver Absolute Maximum Ratings
Symbol
VDD VIN
Parameter
Supply Voltage Input Single Voltage
Ratings 18 5.5
Unit V
Driver Specifications
Symbol
VDD VIN VIN(R) 6 VIN(F) 6 IDDQ IO Coss Ciss VIL VIH TDLY
Parameter
Supply Voltage Input Voltage Input Voltage Rising Edge Input Voltage Falling Edge Quiescent Current Max Output Current Output Capacitance Input Capacitance Input Low Input High Time Delay (throughput)
Min 8 1.8 0.8
Typ 3
Max
Unit V ns A A pF
18
2.2 1.2 200 8.5 2500 3
0.8 1.9 38
1.0 2.2
V ns
Driver Specifications
Symbol
tr tf TD
TJ = 25C unless otherwise specified
Test Conditions
15VDD 15VDD
2,4
Parameter
Rise Time 2,3 Fall Time 2,3 Prop. Delay Symmetry 1
Min
RL
Typical
CL
Max
Unit
2-2006 050-4913 Rev A
3.1 2.8 33 1.2
7.5 7.5 38
ns %
15V 15VDD 3
APT Website - http://www.advancedpower.com
MOSFET Absolute Maxumum Ratings
Symbol
VDSS ID RDS(on)
DRF1200
Min Typ
1000 13 0.90
Parameter
Drain-Source Voltage Continuos Drain Current THS = 25C Drain-Source On State Resistance
Max
Unit V A Unit pF
Dynamic Characteristics
Symbol
Ciss Coss Crss
Parameter
Input Capacitance Output Resistance Reverse Transfer Capacitance
Min
Typ
2000 165 75
Max
Thermal Characteristics
Symbol
RJC TJ PD PDC
Characteristic
Junction to Case Thermal Resistance Operating and Storage Junction Temperature Maximum Power Dissipation Total Power Dissipation @ TC = 25C
Ratings 0.13 175 >100 1050
Unit C/W C W
1. 2 3 4 5 6
APT reserves the right to change, without notice, the specifications and information contained herein.
Test curcuit show on page 3. All measurements were made with the Anti-Ring circuit activated unless noted. Symmetry is the percent difference in high and low FWHM times with a 50% duty cycle square wave input. RL = 50, CL = 3000pF 10% - 90% See Test Circuit 50% - 50%, see Test Circuit VDD = 18V, CL = 3000pF, F = 10MHz Performance specified with this input.
Figure 1, DRF1200 Simplified Ciruit Diagram
A Simplified DRF1200 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitors (C1-C8), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimal the gate drive to the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input, Kelvin signal ground and the Anti-Ring Function, Provide improved stability and control in Kilowatt to Multi-Kilowatt, High Frequency applications. The IN pin is the input for the control signal and is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for ring abatement. The P channel and N channel power drivers provide the high current to the gate of the MOSFET and the MOSFET drain is attached to the OUT pin (9).
2-2006
Driver Control Logic
Driver Output LOW Driver Output HIGH
Rev A
In (4) HIGH Driver In (4) LOW Driver
MOSFET OFF Drain (9) HIGH MOSFET ON Drain (9) LOW
050-4913
The FUNCTION, FN, pin (3) is used to disable the Anti-Ring function. It is recommended that the device be operated with this function enabled. Func. = Hi (+5V or Float) Anti-Ring on, Func. = Low (0V or GND.) Anti-ring off. On the Output side are the POWER GROUND connections pin 8 and pin 10. The DRAIN connection is pin 9. It is suggested that output currents be restricted to these pins by design.
DRF1200
Figure 2, Test Circuit
The Test Circuit illustrated above was used to evaluate the DRF1200 (available as an evaluation Board DRF1200 EVAL). The input control signal is applied to the DRF1200 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The FN pin is very sensitive and unwanted signals can cause erratic behavior, Therefore FN pin is heavily by-passed on the Evaluation board, see FN (3) above. The +VDD inputs (2,6) are By-Passed (C1-C3, C5-C7), this is in addition to the internal bypassing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. A 50 (R4) load is used evaluate the output performance of the DRF1200.
050-4913
Rev A
2-2006
DRF1200
Figure 3, Drain & Current Waveforms
Figure 4, Drain Fall Time
In Figure 3 we see a drain voltage fall of 800V and the current rise of 13.6A in a 50 Load. The drain voltage fall time is 3.4ns 10% to 90% as shown in Figure 4.
Figure 5, Typical Capacitance vs. Drain-to-Source Voltage
Figure 6, Typical Maximum Safe Operating Area
Rev A
2-2006
Figure 7, Maximum Effective Transient Thermal Impedance, Junction-to -Case vs. Pulse Duration
050-4913
DRF1200
0.275
0.200 10
SOURCE GND
0.369 9
DRAIN
0.200 8
SOURCE GND
0.275
.090 Gap Typ.
0.300
.115 in. Clear 4 Places
5600 5600 5600 5600
APT DRF1200
0.750
5600 5600 5600 5600
1.00
0.300 1 GND +VDD 0.06 2 3 4 5 6 7 GND
.050 Gap Typ. .005in. Typ. Half Hard Copper Gold Plated
0.100
+VDD FN
IN SG +VDD 0.04 1.25 1.500
0.040 0.300
Figure 8, DRF1200 Mechanical Outline
050-4913
Rev A
2-2006
DRF1200
Vds Monitor FN By-Pass HV By-Pass Capacitors Load Resistors +Vdd By-Pass Capacitors
This Section Configured by User Control In 50 Terminator Control In +Vdd By-Pass Capacitors Decoupling Resistors
Figure 9, DRF1200 Eval Board The DFR1200 is a high power device and must have adequate cooling for full power operation Evaluation Boards are provided to facilitate the circuit design process by allowing the end user to quickly evaluate the performance of our components under a specific and single set of conditions. They are not intended to be used as a sub assembly in any final product(s). Care has been taken to insure that the Evaluation Boards are assembled to correctly represent the test circuit included in the component data sheet. There is no warranty of these Evaluation Boards beyond workmanship and materials.
050-4913
Rev A
2-2006
DRF1200
5.5 5.196 Advanced Power Technology DRF1200 0.900
4 holes .150 dia.
3.50 3.196 1.7
RE 12/06/05 revD 1.425 1.145
See DRF1200 mechanical drawing for physical dimension details
PCB material - .062 FR4
Figure 10, DRF1200 Eval Board Mechanical
050-4913
Rev A
2-2006
DRF1200 Mounting instructions for Flangeless Packages Heat sink mounting of any device in the Flangeless Package family follows the same process details outlined in this document.
3 T3 Package 1
Torque screws in 1 -2-3-4 Sequence
2
4
Stress Relief "S" Bend On all leads
4-40 Socket head SS Screws . Torque to 8in.lb. #4 Flat Washer
2. The BeO surface of the device must be free of any foreign objects or material. 3. The BeO surface must be coated with a thin and uniform film of thermal compound. 4. For commercial manufacturing the suggested method for thermal compound application is to apply the compound using a screen printer. This process insures consistent and repeatable performance with minimum effort. Mechanical Attachment: 1. The four screws (1-2-3-4), as shown in Figure 11, should be installed and seated, then torqued to one-half the specification, in the sequence shown. First screw 1 then screw 2, 3 and 4. 2. Then complete the process by tightening to the full specification in the same manner. 3. The torque spec is 8in.lb. 1lb. (0.9Nm) Lead Attachment: 1. The leads may now be soldered to the PCB 2. Maximum lead temperature must not exceed 300C for 10s. 3. For lead free use 96.5 % tin, 3% silver, and 0.5% copper. 4. Non-lead Free use 2% Silver, 62% Tin, 36% lead (sn62).
PCB
PCB
Thermal Compound
Figure 11, Top and Side View of a T3 device Heat Sink Surface: 1. The heat sink surface should be smooth, free of nicks and burs; in addition it should be flat to .001in./in TIR, (Total Indicator Run out) and be finished to ~ 68 CLA, (Center Line Average). 2. Must be free of solder balls, metal shavings and any foreign objects or material.
Stress Relief "S" Bend On all leads
PCB
2-2006
Figure 12, Stress Relief bend Device Preparation: 1. The leads should be prepared with an "s" bend, as shown in Figure 10 prior to mounting on the heat sink
050-4913
Rev A

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